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APRIL 1995 MA5104
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MA5104
RADIATION HARD 4096 x 1 BIT STATIC RAM
The MA5104 4k Static RAM is configured as 4096 x 1 bits and manufactured using CMOS-SOS high performance, radiation hard, 3m technology. The device has separate input and output terminals controlled by Chip Select and Write Enable. The design uses a 6 transistor cell and has full static operation with no clock or timing strobe required. Address input buffers are deselected when Chip Select is in the HIGH state. Operation Mode Read Write Standby CS L L H WE H L X I/O D OUT D IN High Z ISB2 Power ISB1
FEATURES
s 3m CMOS-SOS Technology s Latch-up Free s Fast Access Time 90ns Typical s Total Dose 106 Rad(Si) s Transient Upset >1010 Rad(Si)/sec s SEU <10-10 Errors/bitday s Single 5V Supply s Three State Output s Low Standby Current 10A Typical s -55C to +125C Operation s All Inputs and Outputs Fully TTL or CMOS Compatible s Fully Static Operation
Figure 1: Truth Table
Figure 2: Block Diagram
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CHARACTERISTICS AND RATINGS
Symbol VCC VI TA TS Parameter Supply Voltage Input Voltage Operating Temperature Storage Temperature Min. -0.5 -0.3 -55 -65 Max. 7 VDD+0.3 125 150 Units V V C C Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functlonal operation of the device at these condltions, or at any other condition above those indicated in the operations section of this specification, is not Implied Exposure to absolute maxlmum rating conditions for extended perlods may affect device reliability.
Figure 3: Absolute Maximum Ratings
Notes for Tables 4 and 5: 1. Characteristics apply to pre radiation at TA = -55C to +125C with VDD = 5V 10% and to post 100k Rad(Si) total dose radiation at TA = 25C with VDD = 5V 10% (characteristics at higher radiation levels available on request). 2. Worst case at TA = +125C, guaranteed but not tested at TA = -55C. GROUP A SUBGROUPS 1, 2, 3. Symbol VDD VlH VlL VOH VOL ILI ILO IPUI IPDI IDD ISB1 ISB2 Parameter Supply voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current (note 2) Output Leakage Current (note 2) Input Pull-Up Current Input Leakage Current Power Supply Current Selected Supply Current Standby Supply Current Conditions IOH1 = -1mA IOL = 2mA All inputs except CS Output disabled, VOUT = VSS or VDD VIN = VSS on CS input only VIN = VSS on CS input only fRC = 1MHz, CS = 50% mark:space CS = VSS Chip disabled Min. 4.5 VDD/2 VSS 2.4 Typ. 5.0 12 25 50 Max. 5.5 VDD 0.8 0.4 10 20 -100 5 16 35 3000 Units V V V V V A A A A mA mA A
Figure 4: Electrical Characteristics
Symbol VDR IDDR
Parameter VCC for Data Retention Data Retention Current
Conditions CS = VDR CS = VDR, VDR = 2.0V
Min. 2.0 -
Typ. 30
Max. 2000
Units V A
Figure 5: Data Retention Characteristics
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AC CHARACTERISTICS
Conditions of Test for Tables 5 and 6: 1. Input pulse = VSS to 3.0V. 2. Times measurement reference level = 1.5V. 3. Transition is measured at 500mV from steady state. 4. This parameter is sampled and not 100% tested. Notes for Tables 6 and 7: Characteristics apply to pre-radiation at TA = -55C to +125C with VDD = 5V10% and to post 100k Rad(Si) total dose radiation at TA = 25C with VDD = 5V 10%. GROUP A SUBGROUPS 9, 10, 11. Symbol TAVAVR TAVQV TELQV TELQX (4) TELQZ (4) TAXQX Parameter Read Cycle Time Address Access Time Chip Select to Output Valid Chip Select to Output Active Chip Select to Output Tri State Output Hold from Address Change Min 135 10 10 10 Max 135 135 50 Units ns ns ns ns ns ns
Figure 6: Read Cycle AC Electrical Characteristics
Symbol TAVAVW TAVWL TWLWH TWHAV TDVWH TNHDX TWLQZ (4) TELWL TELWH TAVWH TWHQX (4)
Parameter Write Cycle Tlme Address Set Up Time Write Pulse Width Write Recovery Time Data Set Up Time Data Hold Time Write Enable to Output Tri State Chip Selection to Write Low Chip Selection to End of Write Address Valid to End of Write Output Active from End to Write
Min 135 10 50 5 35 5 10 25 85 80 5
Max 50 -
Units ns ns ns ns ns ns ns ns ns ns ns
Figure 7: Write Cycle AC Electrical Characteristics
Symbol CIN COUT
Parameter Input Capacitance Output Capacitance
Conditions Vl = 0V VO = 0V
Min. -
Typ. 6 8
Max. 10 12
Units pF pF
Note: TA = 25C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured.
Figure 8: Capacitance
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Symbol FT
Parameter Basic Functionality
Conditions VDD = 4.5V - 5.5V, FREQ = 1MHz VIL = VSS, VIH = VDD, VOL 1.5V, VOH 1.5V TEMP = -55C to +125C, GPS PATTERN SET GROUP A SUBGROUPS 7, 8A, 8B
Figure 9: Functionality
Subgroup 1 2 3 7 8A 8B 9 10 11
Definition Static characteristics specified in Tables 4 and 5 at +25C Static characteristics specified in Tables 4 and 5 at +125C Static characteristics specified in Tables 4 and 5 at -55C Functional characteristics specified in Table 9 at +25C Functional characteristics specified in Table 9 at +125C Functional characteristics specified in Table 9 at -55C Switching characteristics specified in Tables 6 and 7 at +25C Switching characteristics specified in Tables 6 and 7 at +125C Switching characteristics specified in Tables 6 and 7 at -55C
Figure 10: Definition of Subgroups
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TIMING DIAGRAMS
TAVAVR ADDRESS TAVQV TELQV CS TELQX
HIGH IMPEDANCE
TAXQX
TEHQZ
DATA OUT
DATA VALID
1. WE is high for Read Cycle. 2. Address Vaild prior to or coincident with CS transition low.
Figure 11a: Read Cycle 1
TAVAVR ADDRESS TAVQV DATA OUT TAXQX
DATA VALID
1. WE is high for Read Cycle. 2. Device is continually selected. CS low.
Figure 11b: Read Cycle 2
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TAVAVW
ADDRESS
TAVWH TAVWL
(4)
TWHAV (3) TWLWH (2)
WE
TAXQX TWLQZ TELWL
(7)
TWLQH
(5) (6)
DATA OUT
HIGH IMPEDANCE
TDVWH
DATA IN DATA VALID
TWHDX
TELWH
CS
1. WE must be high during all address transitions. 2. A write occurs during the overlap (TWLWH) of a low CS, a high CE and a low WE. 3. TWHAV is measured from either CS or WE going high or CE going low, whichever is the earlier, to the end of the write cycle. 4. If the CS low transition occurs simultaneously with, or after, the WE low transition, the output remains in the high impedance state. 5. DATA OUT is the write data of the current cycle, if selected. 6. DATA OUT is the read data of the next address,if selected. 7. TELWL must be met to prevent memory corruption.
Figure 12: Write Cycle
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OUTLINES AND PIN ASSIGNMENTS
D
9
1
10
18
W Seating Plane ME
A1 A
H e b Z 15
C e1
Ref A A1 b c D e e1 H Me Z W
Millimetres Min. 0.38 0.35 0.20 4.44 Nom. 2.54 Typ. 8.13 Typ. Max. 5.715 1.53 0.59 0.36 23.11 5.38 8.28 1.27 1.53 Min. 0.015 0.014 0.008 0.175 -
Inches Nom. 0.100 Typ. 0.300 Typ. Max. 0.225 0.060 0.023 0.014 0.910 0.212 0.326 0.050 0.060
A0 A1 A2 A3 A4 A5 Dout WE Vss 1 2 3 4 5 6 7 8 9 Top View 18 Vdd 17 A6 16 A7 15 A8 14 A9 13 A10 12 A11 11 Din 10 CS
XG406
Figure 13: 18-Lead Ceramic DIL (Solder Seal) - Package Style C
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M b
D
Z
e L A c
ME
A1
Ref A A1 b
Inches Min. 0.026 0.015 0.003 0.590 0.265 0.395 0.30 0.005 Nom. 0.050 Max. 0.105 0.019 0.006 0.610 0.305 0.405 0.045
Pin 1
c D e L M Me Z
XG537
Vdd 24 A6 23 A7 22 A8 21 NC 20 NC 19 A9 18 A10 17 A11 16 Din 15 NC 14 CS 13 Bottom View
1 NC 2 A0 3 A1 4 A2 5 A3 6 A4 7 A5 8 Dout 9 NC 10 WE 11 Vss 12 NC
Figure 14: 24-Lead Ceramic Flatpack (Solder Seal) - Package Style F
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Func t ion A0 A1 A2 A3 A4 A5 DOUT WEB VSS CSB DIN A11 A10 A9 A8 A7 A6 VDD
P a c k a ge O pt ion F C 2 3 4 5 6 7 8 10 11 13 15 16 17 18 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
V ia R R R R R R R R Direct R R R R R R R R Direct
S t a t ic 1 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 5V
Burnin S t a t ic 2 5V 5V 5V 5V 5V 5V 5V 5V 0V 5V 5V 5V 5V 5V 5V 5V 5V 5V
Dy na mic F0 F1 F2 F3 F4 F5 LOAD F12 0V 0V F13 F11 F10 F9 F8 F7 F6 5V
Ra dia t ion 5V 5V 5V 5V 5V 5V 5V 5V 0V 5V 5V 5V 5V 5V 5V 5V 5V 5V
1. F0=150KHz, F1=F0/2, F2=F0/4, F3=F0/8 etc. 2. Burnin R=1k 3. Radiation R=10k
Figure 15: Burnin and Radiation Configuration
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RADIATION TOLERANCE
Total Dose Radiation Testing For product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. The sample devices will be subjected to the total dose radiation level (Cobalt-60 Source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. Electrical tests, pre and post irradiation, will be read and recorded. GEC Plessey Semiconductors can provide radiation testing compliant with MIL-STD-883 test method 1019, Ionizing Radiation (Total Dose).
Total Dose (Function to specification)* Transient Upset (Stored data loss) Transient Upset (Survivability) Neutron Hardness (Function to specification) Single Event Upset** Latch Up
1x105 Rad(Si) 5x1010 Rad(Si)/sec >1x1012 Rad(Si)/sec >1x1015 n/cm2 3.4x10-9 Errors/bit day Not possible
* Other total dose radiation levels available on request ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
Figure 16: Radiation Hardness Parameters
SINGLE EVENT UPSET CHARACTERISTICS
UPSET BIT CROSS-SECTION (cm2/bit)
Ion LET (MeV.cm2/mg)
Figure 17: Typical Per-Bit Upset Cross-Section vs Ion LET
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ORDERING INFORMATION
Unique Circuit Designator
Radiation Tolerance S L C R Radiation Hard Processing 30 kRads (Si) Guaranteed 50 kRads (Si) Guaranteed 100 kRads (Si) Guaranteed
MAx5104xxxxx
QA/QCI Process (See Section 9 Part 4)
Test Process (See Section 9 Part 3) Package Type C F Ceramic DIL (Solder Seal) Flatpack (Solder Seal) Assembly Process (See Section 9 Part 2)
Reliability Level L C D E B S Rel 0 Rel 1 Rel 2 Rel 3/4/5/STACK Class B Class S
For details of reliability, QA/QC, test and assembly options, see `Manufacturing Capability and Quality Assurance Standards' Section 9.
HEADQUARTERS OPERATIONS
CUSTOMER SERVICE CENTRES
GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire, SN2 2QW, United Kingdom. Tel: (01793) 518000 Fax: (01793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017, 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576
* FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07 * GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55 * ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 * JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 * NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023 * SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 * SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 * TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260 * UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK
Tel: (01793) 518527/518566 Fax: (01793) 518582 These are supported by Agents and Distributors in major countries world-wide. (c) GEC Plessey Semiconductors 1995 Publication No. DS3580-3.2 April 1995 TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
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